Abstract :
Floor planning is that the very basic stage in VLSI physical design for classified building module design
methodology. The floorplanning is employed to calculate to the relative location of blocks within the fixed outline.
The planning obscurity is increasing and therefore the circuit size is obtaining additional. Thus ultimately area of the
circuit gets rise and harder to optimize the Wirelength and area. This leads the terribly high attention to tend for
VLSI floorplanning. So our objective is to attenuate the chip area and fix the modules or blocks within the fixed
outline constraints. During this paper we focus the particle swarm optimisation (PSO) methodology to achieve global
solution for fixed outline constraints for this we tend to taken MCNC and GSRC benchmark circuits.
Keyword :
VLSI Floor planning, Particle Swarm Optimization (PSO), Chip area.