Article PDF :

Veiw Full Text PDF

Article type :

Original article

Author :

Aleksandr Barkalov,Larysa Titarenko,Yaroslav Vizor,Aleksandr Matvienko

Volume :

1

Issue :

2

Abstract :

Introduction. The model of a finite state machine is widely used for describing behavior of different sequential blocks, such as control units. It is possible that control units possess output signals having both types of Mealy and Moore automata. A model of the combined automaton can be used to synthesize such devices. When the automaton circuit is implemented, it is necessary to optimize its characteristics such as hardware amount. The methods of this task solution depend significantly on logic elements used to implement circuits. In this article, we propose a method of reducing hardware in the circuit of combined automaton implemented with ASIC. In this case, the circuit is implemented using customized matrix circuits. The proposed method allows reducing the chip area occupied by the circuit of the automaton. The method is based on the expansion of the matrix that generates circuit product terms of the systems of input memory functions and output functions of the combined automaton. The additional part of the matrix generates terms for output functions of Moore automaton. It allows reduction of the chip area as compared to the area of the two-level circuit of the combined automaton. The purpose of the article is to show that the division of circuit matrices allows reducing the resulting matrix area. The hardware amount is estimated for both trivial automaton structure and for the proposed approach. They are determined in conventional units of area. Results. The method is proposed based on the expansion of the matrix of terms. Using an example, it is shown how to execute the steps of the proposed method. To increase the method efficiency, it is proposed to use a special state assignment that minimizes the number of terms in the systems of Boolean functions of outputs with Moore type. The conducted investigations show that the proposed method allows for reducing the resulting ASIC area from 10% to 26%. The gain increases with the growth of the automaton complexity. Conclusions. A comparison of the proposed method with some known synthesis methods shows that the expansion of the matrix of terms for systems of input memory functions and output functions allows reducing the chip area occupied by the circuit of the combined automaton.