Abstract :
Floor planning is that the terribly central stage in VLSI physical style for class conscious building
module style methodology. Floorplanning affords early response that evaluates architectural choices, approximation
of chip space, estimates delay, interconnect length and congestion caused by wiring. As technology
advances, style complexness is increasing and therefore the circuit size is obtaining larger. Thus space of the circuit
gets increase and tougher to minimizing the interconnect length. The VLSI floorplanning is that
the NP onerous downside. So it’s horribly troublesome to seek out the best solution. During this paper we tend to take
into account, a multi-objective genetic algorithmic program primarily based floorplanning has been developed with
novel crossover operators to handle the multi-objective floorplanning for Very Large Scale Integration application
specific integrated circuits (VLSI ASICs). The Genetic algorithmic program (GA) approach is employed for
minimizing the whole space and interconnects length.
Keyword :
VLSI floor planning, Genetic Algorithm, Area and Interconnect length