Abstract :
Background: This paper describes about correlator architectures with different VLSI optimization techniques such
as parallel processing and pipelining. Both of these techniques are used to reduce the power consumption and to
achieve high speed. Objective: To achieve high speed and low power consumption, VLSI optimization techniques
such as parallel processing and pipelining technique is used. Results: Simulation is done using Xilinx ISE 13.2 tool
with Verilog HDL (Verification Logarithmic Hardware Description Language) and it has been synthesized on
Kintex7 (xc7k70t-fbg676) FPGAs for the multiplier less correlator and pre-compute correlator. When compared to
parallel pre-compute correlator, parallel pre-compute correlator with pipelining reduces the delay by 20.77%.
Conclusion: Up to certain limit pipelining provides significant performance gains with little increase in chip area. It
also reduces glitching in the circuit. Throughput beyond that acheivable by pipelining can be attained by parallel
architectures.
Keyword :
Optimization, Parallel Processing, Pipelining, Correlator.