Abstract :
The goal of this work is to develop DRAM controller between Main Processor and the main memory for fast interfacing of the data and this is achieved with the help of a new Super Harvard type of interfacing parallel interfacing for the data, program data and instructions, also the proposed work used four stage pipelining to achieve high throughput and high speed interfacing. Vertex Corse grain FPGA has been used for the design of the work hence the area can be minimized also the mix modeling architecture is been used. The architecture is designed in Xilinx EDA using Verilog HDL and verification of the design is been done of ISE. The result in terms of speed and area are found better.
Keyword :
SDRAM, DDR, FPGA, RTS