Abstract :
In this paper we have proposed efficient designs of low power high speed D latch designed using stacked inverter and sleep transistor based on 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in the circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product. Lalitesh Singh | Surendra Bohra "Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: https://www.ijtsrd.com/papers/ijtsrd14138.pdf Paper URL: http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14138/design-of-low-power-high-speed-d-latch-using-stacked-inverter-and-sleep-transistor-at-32nm-cmos-technology/lalitesh-singh
Keyword :
CMOS, Clock, Latch, Power Delay Product, MOSFET